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6.1 Buffer memory
BFM#16: The D/A conversion data of the channel specified with BFM#17 (digital value) is written.
The D/A data is written in binary in order of the lower 8bit and higher 4bit and divided into two
portions.
BFM#17: b0•••The D/A conversion of CH2 begins by changing of 1→0.
b1•••The D/A conversion of CH1 begins by changing of 1→0.
b2•••The lower eight bit data for the D/A conversion is held by changing of 1→0.
Write data in the above-mentioned buffer memory by "8. Program example".
BFM
number
b15 to b8 b7 to b3 b2 b1 b0
#0 to #15 Reserved
#16 Reserved Digital source data for output (8 bit)
#17 Reserved
Lower data holding
bit
CH1 D/A
conversion
beginning
CH2 D/A
conversion
beginning
#18 or more Reserved
模擬量輸入擴展板 FX2N-2AD-BD
模擬量輸入輸出模塊 FX2N-5A
PLC FX2N-48MR-UA1/UL
存儲卡 FX2N-ROM-E1
模擬量輸入模塊 FX2N-4AD
繼電器輸出模塊 FX2N-8EYR
輸入模塊 FX2N-16EX-ES/UL
輸出擴展板 FX2N-2EYT-BD
PLC FX2N-48MR-DS
輸入模塊 FX2N-16EX
晶體管輸出單元 FX2N-32ET
脈沖輸出模塊 FX2N-10PG
輸入擴展板 FX2N-4EX-BD
PLC FX2N-32MT-001
PLC FX2N-128MR-D
PLC FX2N-16MT-E/UL
PLC FX2N-48MS
輸出模塊 FX2N-16EYT-ESS/UL
模擬量輸入模塊 FX2N-8AD
輸入模塊 FX2N-16EX-C
輸入模塊 FX2N-8EX
PLC FX2N-80MT-DSS
擴展模塊 FX2N-16EYT
PLC FX2N-16MT-ESS/UL
輸入模塊 FX2N-16EXL-C
PLC FX2N-64MR-UA1/UL
PLC FX2N-80MT-001
擴展板 FX2N-8AV-BD
PLC FX2N-32MT-DSS
PLC FX2N-64MT-DSS